Orison
Financiado
igzO-based smaRt Interposer technologieS fOr iNtegrated circuits and pixels
Silicon complementary metal-oxide semiconductor (Si CMOS) technologies are ubiquitous in a plethora of products today employing a multitude of chips. The current challenges of Si chips research and applications are area, power con...
Silicon complementary metal-oxide semiconductor (Si CMOS) technologies are ubiquitous in a plethora of products today employing a multitude of chips. The current challenges of Si chips research and applications are area, power consumption and high-voltage interposing for AR/VR, low-power IoT, high-voltage sensors and actuator interfaces such as MEMS and lab-on-chip.
ORISON’s goal is to develop a scalable toolbox on top of Si CMOS chip technologies for disruptive research activities in ultralow power circuit design, high-voltage interfacing and low-area 3D stacked hybrid pixel engines. The technology platform focuses on a 3D hetero-integration route of Si CMOS and Indium-Gallium-Zinc-Oxide (IGZO) n-type transistors with a 100x lower electron mobility. The game changing nature of ORISON enables innovation on three major pillars: (1) extreme low off-stage leakage currents due to the wide bandgap semiconductor, leading to ultralow power and long retention electronic circuits, (2) the absence of a bulk for IGZO devices, enabling low footprint and high-voltage devices on top of Si CMOS and (3) a 3D technology platform facilitating beyond state-of-the-art circuit and pixel resolutions.
A new hybrid Si pMOS/IGZO cell library will be pioneered targeting ultra-low power consumption because of comparable sub-threshold slopes of both technologies, low off-state leakage currents and individual tuneable threshold voltages by a local backgate. In addition, true cell-level power gating techniques are envisioned to radically reduce the idle power consumption, paving the way to lifetime battery-powered or battery-less wearables and leaf-node IoT.
The novel high-voltage hybrid library impacts positively MEMS and AR/VR applications with unprecedented footprint and power characteristics and enables technology partitioning for smart pixels. The 3D technology also envisions high-resolution pixel engines with refresh-on-demand capacitor-less pixel engines.
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Duración del proyecto: 61 meses
Fecha Inicio: 2023-03-03
Fecha Fin: 2028-04-30
Fecha Fin: 2028-04-30
Línea de financiación: concedida
El organismo HORIZON EUROPE notifico la concesión del proyecto el día 2023-03-03
Línea de financiación objetivo
El proyecto se financió a través de la siguiente ayuda:
ERC-2022-COG:
ERC CONSOLIDATOR GRANTS
Cerrada
hace 2 años
Presupuesto
El presupuesto total del proyecto asciende a
2M€
Líder del proyecto
KATHOLIEKE UNIVERSITEIT LEUVEN
No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico
TRL
4-5
Perfil tecnológico
TRL
4-5