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ULKCOND

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Zero damage Ultra Low K etch using the precursor CONDensation technique

Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an... ver más

31/03/2018

IMEC

161K€

Presupuesto del proyecto: 161K€

Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2018-03-31

MSCA-IF-2015-EF: Marie Skłodowska-Curie Individual F...

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Cerrada hace 9 años

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No hay información privada compartida para este proyecto. Habla con el coordinador.

1 Participantes

IMEC

160.80K€ | Lider

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Duración del proyecto: 24 meses Fecha Inicio: 2016-03-11
Fecha Fin: 2018-03-31

Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 161K€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an overall increase of the resistivity of the conductor and the dielectric’s capacitance, ultimately causing delayed signal transmission (so-called RC delay). In order to decrease the resistivity, Al was replaced by Cu as a conductor. The circuit’s capacitance can be lowered by using materials with lower dielectric permittivity, named low-k’s. Nowadays, the most successful low-k dielectrics are porous organo-silicate glasses, with porosity up to 50%, pore size around 1.5-2 nm and k-values down to 1.8 (k=4.2 for bulk SiO2). Interconnects are nowadays built by the Damascene technique, where the dielectric is first deposited, then locally etched away, followed by metal deposition in the patterned structure and polishing for metal excess removal. Due to their intrinsic porosity, most of processing steps cause low-k damage, amongst which plasma etching is the most damaging. The present proposal aims at understanding and optimizing zero-damage cryogenic etching of low-k materials, compatible with the micro-electronics industry (at temperature above -60°C). Besides the improvement of the etching process and the better understanding of reactions damaging the low-k materials during plasma etching, this work will investigate the phenomenon of micro-capillary condensation into porous materials, which is not widely explored and can lead to other applications in micro-electronics and in other nanotechnology domains. This research project will contribute to enable the so-called 5nm node in future CMOS manufacturing, and as a consequence it will have a wide economic impact. Finally, this research will allow the applicant to extend his technical and project management skills, strengthening his profile for a future career in the semiconductor industry or R&D.

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