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HISTORIC

Financiado

Cerrado

Heterogeneous InP on Silicon Technology for Optical Routing and LogIC

HISTORIC proposes to design, develop and test digital photonic integrated circuits containing a relatively large number of active photonic elements combined with passive elements, for use in e.g. all-optical packet switching for b... ver más

31/12/2011

IMEC

3M€

Presupuesto del proyecto: 3M€

Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 4 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2011-12-31 No tenemos la información de la convocatoria

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Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

4 Participantes

IMEC

0.00€ | Lider

IBM

N.D. | Participante

TU/e

N.D. | Participante

CNRS

N.D. | Participante

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Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 3M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto HISTORIC proposes to design, develop and test digital photonic integrated circuits containing a relatively large number of active photonic elements combined with passive elements, for use in e.g. all-optical packet switching for both datacom and telecom. The building blocks for the digital photonic circuits are ultra-compact gates based on micro-ring or micro-disk lasers, photonic crystal lasers or metallic nanocavity (or plasmonic) lasers. These lasers are fabricated making use of the heterogeneous integration of InP membranes on top of silicon on insulator passive optical circuits. Different approaches for the ultra compact lasers will be investigated, allowing to make use of the high precision growth and processing techniques available to the InP platform, as well as to take advantage of the extreme accuracy of state-of-the-art CMOS processing.Several all-optical flip-flops and gates will be integrated on a single chip, and will be interconnected by short wire waveguides in the SOI structure. The extremely small dimensions of both the flip-flops, gates and their interconnections will result in a competitive footprint of optical packet switches as compared with electronic switches.The targetted ultra small dimensions of the laser-based all-optical flip-flops are expected to result in record low switching times and switching energies. Together with the low propagation losses in the SOI waveguides, this is expected to result in a competitive speed and power consumption of optical packet switches.The possibility of integrating a large number of photonic digital units together, as well as integrating them with compact passive optical routers such as AWGs, opens new perspectives for the design of integrated optical processors or optical buffers. The project will therefore also focus on designing new architectures for such optical processing or buffer chips. Extensive characterisation and system tests will demonstrate the advantage of the new optical approach.

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