Hola,
¿eres nuevo aquí?

Regístrate gratis y conecta tu empresa con financiación pública, partners y proyectos.

Tengo cuenta

Regístrate

Ver video

AnalogCreate

Financiado

Cerrado

Autonomous Creation of Analog Integrated Circuits based on Self Learning of Desi...

Autonomous Creation of Analog Integrated Circuits based on Self Learning of Design Expertise Progress in semiconductor technology and in intelligent data processing are converging today, opening the door to countless smart ICT applications through the Cloud and Internet of Everything, to the people’s benefit in years to c... ver más

31/08/2026

KU Leuven

3M€

Presupuesto del proyecto: 3M€

Líder del proyecto

KATHOLIEKE UNIVERSITEIT LEUVEN No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2021-06-29

ERC-2020-ADG: ERC ADVANCED GRANT

I+D

Cerrada hace 4 años

0% 100% 100%

Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

1 Participantes

KU Leuven

2.50M€ | Lider

Conecta tu I+D

¿Tienes un proyecto y buscas un partner? Gracias a nuestro motor inteligente podemos recomendarte los mejores socios y ponerte en contacto con ellos. Te lo explicamos en este video

Proyectos interesantes

EmpoSoC A Paradigm Change for System-on-Chip Design to Enable Higher... 4M€ Cerrado

i-RISC Innovative Reliable Chip Designs from Low Powered Unreliable... 2M€ Cerrado

Reexen Ultra low cost ultra high efficiency AI processor for enab... 71K€ Cerrado

NOVOFLOP Non Volatile Magnetic Flip Flop 150K€ Cerrado

TEC2009-07859 OPTIMIZACION DEL COMPORTAMIENTO DE CIRCUITOS INTEGRADOS BASA... 225K€ Cerrado

H-3D-SOC 3D IC Design Flow for Hybrid bonding 3D System on Chip 178K€ Cerrado

Duración del proyecto: 62 meses Fecha Inicio: 2021-06-29
Fecha Fin: 2026-08-31

Líder del proyecto

KATHOLIEKE UNIVERSITEIT LEUVEN No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 3M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto Progress in semiconductor technology and in intelligent data processing are converging today, opening the door to countless smart ICT applications through the Cloud and Internet of Everything, to the people’s benefit in years to come. Applications that interact with the physical world (e.g. environmental sensing, healthcare, autonomous vehicles, etc.), also need analog integrated circuits in the cyber-physical or edge layer. But while digital circuits are largely synthesized automatically through software, the analog circuits are mainly still handcrafted in industry with low design productivity. This results in long and error-prone design cycles, and the high development costs jeopardize many potential new ICT applications from ever being realized (e.g. solutions for rare diseases). It becomes even more problematic when moving to advanced technologies below 16 nm CMOS, that come with way more design and layout rules to be dealt with. The showstopper for state-of-the-art analog synthesis tools is that they require design heuristics and constraints to be entered explicitly by designers in order to handle the humongous solution space and to steer the circuit and layout optimizations towards acceptable solutions. The proposed disruptively new approach is to use the self-learning capabilities of advanced machine learning algorithms to self-learn and then exploit the design expertise and constraints from the many available successfully completed designs. Also a true circuit topology synthesis approach will be developed to create a proper (possibly novel) schematic from the target specifications, as well as an innovative formal analog design verification approach based on Quick Error Detection. These innovations will enable for the first time ever to truly autonomously create analog circuits from specifications to fully verified layout without direct input from any designer in the loop, and therefore enable the affordable implementation of many promising ICT applications.

Conecta tu I+D

Entra hoy

¿Olvidé mi contraseña?

Financiación

Empresas

CTIs/Universidades

Proyectos

Investigadores