3D IC Design Flow for Hybrid bonding 3D System on Chip
As the device size is shrunk to its quantum limit, Moore’s law is becoming more difficult to follow. By exploiting the z-direction in the gate, block or system level, three-dimensional (3D) integrated circuit (IC) technology has t...
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Información proyecto H-3D-SOC
Duración del proyecto: 24 meses
Fecha Inicio: 2020-03-26
Fecha Fin: 2022-03-31
Fecha límite de participación
Sin fecha límite de participación.
Descripción del proyecto
As the device size is shrunk to its quantum limit, Moore’s law is becoming more difficult to follow. By exploiting the z-direction in the gate, block or system level, three-dimensional (3D) integrated circuit (IC) technology has the potential to extend Moore’s law. Face-to-face wafer by wafer Hybrid-bonding (H-b) based 3D System-On-Chip (H-3D-SOC) is one of the most promising 3D IC solutions. However, an exclusive IC design flow for H-3D-SOC for high-end processor with parameters of H-b pads from process is not available yet. This proposal aims at developing the first H-3D-SOC IC design flow for a two-tier multi-core processor considering the impact of process variation of H-b, including the geometrical and defects variation, leading to its resistance and capacitance change. Several novel methods will be developed for the H-3D-SOC IC design: machine-learning inspired techniques exploited to guide the top and bottom tiers netlist partitioning; two-tier mutual-aware optimization realized during placement and routing; capacitance coupling between the top metal layers of the two tiers considered during parasitic extraction. Moreover, impact of H-b pad parameter variation will be evaluated from the device level up to the system level: electrical variability modelling for the H-b pad, calibrated by experimental data; incorporating the device model of the pad into the H-3D-SOC based multi-core processor characterized by various industrial benchmarks. To mitigate the H-b variability, the critical H-b pads of higher utilization and larger potential to fail during working can be first identified efficiently by using a heuristic search algorithm and then hardened by attaching a spare pad to each of them. The proposed research will enable the applicant to become an expert of 3D IC design of high-end processors for applications such as AI and cloud computing, having great impact on both academia and industry of semiconductor.