MY-CUBE
Financiado
3D integration of a logic memory CUBE for In Memory Computing
For integrated circuits to be able to leverage the future data deluge coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone...
For integrated circuits to be able to leverage the future data deluge coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this memory wall consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items, as it is the case in the brain. Things may change with the emergence of three key enabling technologies: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic. My-CUBE will leverage them towards a functionality-enhanced system with a tight entangling of logic and memory. Only such a technology can support the scalability of the IMC concept.
Following a holistic approach from the system to the material, My-CUBE unique solution relies on a new class of nano-technology, mixing at the fine-grain level a high capacity of non-volatile resistive memory coupled with new junctionless nanowire transistors 3D-interconnected at low-temperature, to perform data-centric computations. A 3D IMC accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems. This technology that adds smartness to memory/storage will not only be a game changer for artificial intelligence, machine learning, data analytics or any data-abundant computing systems but it will also be, more broadly, a key computational kernel for next low-power, energy-efficient European integrated circuits.
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Duración del proyecto: 60 meses
Fecha Inicio: 2019-03-07
Fecha Fin: 2024-03-31
Fecha Fin: 2024-03-31
Línea de financiación: concedida
El organismo H2020 notifico la concesión del proyecto el día 2024-03-31
Línea de financiación objetivo
El proyecto se financió a través de la siguiente ayuda:
ERC-2018-COG:
ERC Consolidator Grant
Cerrada
hace 6 años
Presupuesto
El presupuesto total del proyecto asciende a
3M€
Líder del proyecto
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENER...
No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico
TRL
4-5
Perfil tecnológico
TRL
4-5
1.95M€ |
Participante