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HORIZON-JU-Chips-2024-1-IA-T2: Topic 2 Focus topic on “High Performance RISC-V Automotive Processors supporting SDV”
Scope:In automotive industry, being no exception from general CPS development trends, SW requirements and HW implementations change over time, which poses a need for an automated process to continuously evaluate different HW SoCs under changing SW requirements. The SDV paradigm provides an efficient mechanism to decouple HW from SW development while preserving system’s integrity and ensuring the propagation of functional and non-functional specifications across system’s abstraction layers. The key role for this decoupling of design concerns is attributed to the HAL in the SDV abstraction model. This focus topic assumes a collaborative agreement with representative European stakeholders on a reference HAL and targets an efficient hardware implementation of the latter based on RISC-V. Proposals need to particularly address but are not limited to the following hardware design aspects:
Sólo fondo perdido 20M €
Europeo
Esta convocatoria está cerrada Esta línea ya está cerrada por lo que no puedes aplicar. Cerró el pasado día 14-05-2024.
Se espera una próxima convocatoria para esta ayuda, aún no está clara la fecha exacta de inicio de convocatoria.
Por suerte, hemos conseguido la lista de proyectos financiados!
Presentación: Consorcio Consorcio: Esta ayuda está diseñada para aplicar a ella en formato consorcio..
Esta ayuda financia Proyectos:

Scope:In automotive industry, being no exception from general CPS development trends, SW requirements and HW implementations change over time, which poses a need for an automated process to continuously evaluate different HW SoCs under changing SW requirements. The SDV paradigm provides an efficient mechanism to decouple HW from SW development while preserving system’s integrity and ensuring the propagation of functional and non-functional specifications across system’s abstraction layers. The key role for this decoupling of design concerns is attributed to the HAL in the SDV abstraction model. This focus topic assumes a collaborative agreement with representative European stakeholders on a reference HAL and targets an efficient hardware implementation of the latter based on RISC-V. Proposals need to particularly address but are not limited to the following hardware design aspects:

Sound tool-agnostic collaboration infrastructure based on joint APIs for automating the continuous assessment process and DSLs for iterating over different HW configurations. This infrastructure promotes and enables new flexible RISC-V based solutions for existing and new use-cases. The pla... ver más

Scope:In automotive industry, being no exception from general CPS development trends, SW requirements and HW implementations change over time, which poses a need for an automated process to continuously evaluate different HW SoCs under changing SW requirements. The SDV paradigm provides an efficient mechanism to decouple HW from SW development while preserving system’s integrity and ensuring the propagation of functional and non-functional specifications across system’s abstraction layers. The key role for this decoupling of design concerns is attributed to the HAL in the SDV abstraction model. This focus topic assumes a collaborative agreement with representative European stakeholders on a reference HAL and targets an efficient hardware implementation of the latter based on RISC-V. Proposals need to particularly address but are not limited to the following hardware design aspects:

Sound tool-agnostic collaboration infrastructure based on joint APIs for automating the continuous assessment process and DSLs for iterating over different HW configurations. This infrastructure promotes and enables new flexible RISC-V based solutions for existing and new use-cases. The planned infrastructure will allow fast and seamless comparison to existing solutions in the different design phases.

Open high-performance RISC-V based automotive processor reference architecture, which can lead to customized instantiations towards specific automotive needs and control domains, including e.g. a superscalar architecture. It should also include a fast context switch with multi-threading support and fast deterministic interrupt/execution response.

Integrated vector unit(s) including custom extensions as e.g. DSP, AI, networking, etc. These should be scalable with chained registers and out-of-order execution.

Co-processor interface for special VPU and accelerators

Safety and security elements, extended to memory and interconnect. This should include spatial and temporal redundancy for temporary and permanent faults and ASIL certification. Security features should include secure enclave and potentially execution guard. Focus should also be on micro-architectural protection for side-channel attacks and SESIP certifications.

Exploration of different on-chip and off-chip interconnect solutions based on existing SotA (e.g. AMBA) or new developments (e.g. chiplets)

Virtualization support with Hypervisor.

Definition and adoption of standardised data formats, interfaces (APIs) and improved interoperability.

Mechanisms to capture and manage, from the software level, fuctional as well as non-functional characteristics of possible integration with SDV modules with particular focus on real-time operation, low power dissipation, handling of (precise) computational exceptions and interrupts.

Benchmarks and workloads for incremental hardware development. These must be usable on COTS HW, FPGA prototypes, simulators as well as emulators and must be also applicable for bare-metal and to top of full SW stacks, including hypervisors and RTOS. Multiple levels of incremental evaluations should be also supported. Finally, a trade-off between representativeness of the software and confidentiality constraints must be made.

Although the development of design software and tools is not a primary subject of this focus topic, efforts and resources needed to develop software enabling or facilitating the design of any of the essential elements of the hardware platform shall be eligible for funding

The consortium should be coordinated by a leading European industrial actor of the automotive industry value chain, or by a neutral organisation well established in the sector . The consortium must include: 

a representative number of European semiconductor companies with headquarters in several Member States; 

a representative number of European tier-1 automotive suppliers and technology companies with headquarters in several Member States;

a representative number of European OEMs of motorised vehicles (passenger cars, trucks, buses, motor cycles) with headquarters in several Member States; 

innovative SMEs across the value chain; 

universities and research and technology organisations bringing the newest advances in relevant digital and other technologies and/or acting act as neutral mediators. 

Proposals are encouraged:

To allocate tasks to cohesion activities with the projects selected under the call HORIZON-KDT-JU-2023-3-CSA Topic 3 on Coordination of the European software-defined vehicle platformon and the call HORIZON-KDT-JU-2023-2-RIA Topic 2 on Hardware abstraction layer for a European Vehicle Operating System.

To allocate tasks to cohesion activities with the projects selected under the previous calls HORIZON-KDT-JU-2021 and -2022 (TRISTAN & ISOLDE)

To allocate tasks to cohesion activities with the [call 2024 SDV].

To allocate tasks to cohesion activities with the [related CCAM and 2ZERO projects].


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Temáticas Obligatorias del proyecto: Temática principal: The text outlines a focus on the development of an efficient Hardware Abstraction Layer (HAL) in the System Design Verification (SDV) paradigm for automotive systems, focusing on the decoupling of hardware from software development. Proposals should address various hardware design aspects, particularly targeting the implementation of a reference HAL based on RISC-V for automotive processors.
Electronics Automotive Engineering

Características del consorcio

Ámbito Europeo : La ayuda es de ámbito europeo, puede aplicar a esta linea cualquier empresa que forme parte de la Comunidad Europea.
Tipo y tamaño de organizaciones: El diseño de consorcio necesario para la tramitación de esta ayuda necesita de:

Características del Proyecto

Requisitos de diseño: *Presupuesto para cada participante en el proyecto
Requisitos técnicos: The expected impacts of the project include developing an automated process to evaluate different hardware System-on-Chips (SoCs) under evolving software requirements, leveraging the System Design Verification (SDV) paradigm to separate hardware from software. Key goals involve creating a collaborative infrastructure for flexible RISC-V solutions, designing a high-performance RISC-V processor architecture for automotive applications, integrating vector units with custom extensions like DSP and AI, ensuring safety and security with redundant elements, exploring interconnect solutions, implementing virtualization support, enhancing interoperability, and managing functional and non-functional characteristics efficiently. The project aims to facilitate incremental hardware development with benchmarks for various testing environments while maintaining the balance between software representativeness and confidentiality requirements. The project consortium involves European semiconductor companies, automotive suppliers, OEMs, SMEs, and research organizations to advance hardware design and enable software development in the automotive industry. The project aligns with other initiatives focusing on hardware abstraction layers and software-defined vehicle platforms, demonstrating a collaborative approach to technological innovation in the automotive sector. The expected impacts of the project include developing an automated process to evaluate different hardware System-on-Chips (SoCs) under evolving software requirements, leveraging the System Design Verification (SDV) paradigm to separate hardware from software. Key goals involve creating a collaborative infrastructure for flexible RISC-V solutions, designing a high-performance RISC-V processor architecture for automotive applications, integrating vector units with custom extensions like DSP and AI, ensuring safety and security with redundant elements, exploring interconnect solutions, implementing virtualization support, enhancing interoperability, and managing functional and non-functional characteristics efficiently. The project aims to facilitate incremental hardware development with benchmarks for various testing environments while maintaining the balance between software representativeness and confidentiality requirements. The project consortium involves European semiconductor companies, automotive suppliers, OEMs, SMEs, and research organizations to advance hardware design and enable software development in the automotive industry. The project aligns with other initiatives focusing on hardware abstraction layers and software-defined vehicle platforms, demonstrating a collaborative approach to technological innovation in the automotive sector.
¿Quieres ejemplos? Puedes consultar aquí los últimos proyectos conocidos financiados por esta línea, sus tecnologías, sus presupuestos y sus compañías.
Capítulos financiables: Los capítulos de gastos financiables para esta línea son:
Personnel costs.
Subcontracting costs.
Purchase costs.
Other cost categories.
Indirect costs.
Madurez tecnológica: La tramitación de esta ayuda requiere de un nivel tecnológico mínimo en el proyecto de TRL 6:. Representa un paso importante en demostrar la madurez de una tecnología. Se construye un prototipo de alta fidelidad que aborda adecuadamente las cuestiones críticas de escala, que opera en un entorno relevante, y que debe ser a su vez una buena representación del entorno operativo real. + info.
TRL esperado:

Características de la financiación

Intensidad de la ayuda: Sólo fondo perdido + info
Fondo perdido:
Para el presupuesto subvencionable la intensidad de la ayuda en formato fondo perdido podrá alcanzar desde un 70% hasta un 100%.
The funding rate for IA projects is 70 % for profit-making legal entities and 100 % for non-profit legal entities. The funding rate for IA projects is 70 % for profit-making legal entities and 100 % for non-profit legal entities.
Garantías:
No exige Garantías
No existen condiciones financieras para el beneficiario.

Información adicional de la convocatoria

Efecto incentivador: Esta ayuda no tiene efecto incentivador. + info.
Respuesta Organismo: Se calcula que aproximadamente, la respuesta del organismo una vez tramitada la ayuda es de:
Meses de respuesta:
Muy Competitiva:
No Competitiva Competitiva Muy Competitiva
El presupuesto total de la convocatoria asciende a
Presupuesto total de la convocatoria.
Proyectos financiables en esta convocatoria.
Minimis: Esta línea de financiación NO considera una “ayuda de minimis”. Puedes consultar la normativa aquí.
Certificado DNSH: Los proyectos presentados a esta línea deben de certificarse para demostrar que no causan perjuicio al medio ambiente. + info

Otras ventajas

Sello PYME: Tramitar esta ayuda con éxito permite conseguir el sello de calidad de “sello pyme innovadora”. Que permite ciertas ventajas fiscales.
Deducción I+D+i:
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La empresa puede aplicar deducciones fiscales en I+D+i de los gastos del proyecto y reducir su impuesto de sociedades. + info