NegCap
Financiado
Negative capacitor based on a ferroelectric nano dot
One of the most exciting proposed solutions to the approaching limit of down-scaling in microelectronics (so-called end of Moore’s law) consists of the use of negative capacitors, [NegCap]s.
When a NegCap is placed between t...
One of the most exciting proposed solutions to the approaching limit of down-scaling in microelectronics (so-called end of Moore’s law) consists of the use of negative capacitors, [NegCap]s.
When a NegCap is placed between the gate and the channel of a FET (field-effect transistor), the applied voltage on the gate is strongly amplified on the channel. Therefore, it is possible to reduce substantially the applied gate voltage, yet keeping the voltage on the gate sufficiently high for on/off switching of the FET.
To continue the scaling down of basic electronic components such as FET, reduction of the applied voltage is essential in order to avoid overheating due to the too high power dissipation in the ultra high-density circuits. On the other hand, due to fundamental laws of physics, a minimum voltage of 60mV/decade is necessary for operation of the FET with currently available technologies. A way to solve these conflicting needs is to reduce the gate voltage and in parallel use a NegCap that will amplify the voltage on the channel.
But how to get a negative capacitor? In 2008 Salahuddin and Datta proposed to make NegCap using a ferroelectric capacitor. However, so far, experimental attempts failed to show the stable negative capacitance necessary for the voltage amplification on the FET gate. The key problem is that the ferroelectric splits into domains, which cancels the stabilized negative capacitance effect.
In our ERC-AdG project (MOBILE-W), we conceived a concept, supported by theory and modelling, that allows the fabrication of negative capacitors in which splitting to domains is prohibited. Here we aim to demonstrate this experimentally providing proof of concept, and find suitable framework and partners to translate our concept into commercial products. We believe that this will solve one of the major road-blocks for further scaling down of microelectronic circuits.
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Duración del proyecto: 18 meses
Fecha Inicio: 2018-04-23
Fecha Fin: 2019-10-31
Fecha Fin: 2019-10-31
Línea de financiación: concedida
El organismo H2020 notifico la concesión del proyecto el día 2019-10-31
Línea de financiación objetivo
El proyecto se financió a través de la siguiente ayuda:
ERC-2017-PoC:
ERC-Proof of Concept
Cerrada
hace 7 años
Presupuesto
El presupuesto total del proyecto asciende a
150K€
Líder del proyecto
TEL AVIV UNIVERSITY
No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico
TRL
4-5
Perfil tecnológico
TRL
4-5
557.35K€ |
Participante