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NaNoC

Financiado

Cerrado

Nanoscale Silicon Aware Network on Chip Design Platform

The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems b... ver más

31/12/2012

UPV

4M€

Presupuesto del proyecto: 4M€

Líder del proyecto

UNIVERSITAT POLITÈCNICA DE VALÈNCIA No se ha especificado una descripción o un objeto social para esta compañía.

Total investigadores 688

Fecha límite participación Sin fecha límite de participación.

Ver 6 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2012-12-31 No tenemos la información de la convocatoria

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Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

6 Participantes

UPV

0.00€ | Lider

Unife

N.D. | Participante

IFAG

N.D. | Participante

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Líder del proyecto

UNIVERSITAT POLITÈCNICA DE VALÈNCIA No se ha especificado una descripción o un objeto social para esta compañía.

Total investigadores 688

Presupuesto del proyecto 4M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto The NaNoC project aims at developing an innovative design platform for future Network-on-Chip (NoC) based multi-core systems. This NaNoC design platform intends to master the design complexity of advanced microelectronic systems by enabling strict component oriented architectural design. A compositional approach to NoC design in future multi-core chips is out of the reach of current design methods and tools due to new design constraints. Requirements for co-design with high-level platform management frameworks facilitates a need for enhanced dynamism and flexibility in NoC composition (e.g., virtualization, power management, thermal management, application management). On the other hand, a higher degree of uncertainty originating from nanoscale IC fabrication technologies raises the need to build reliable systems out of unreliable components.The NaNoC design platform provides design methods and prototype tools to cope with both challenges and to make NoCs a mainstream interconnect backbone for effective system integration. The platform enables NoC component assembly at each layer of the design hierarchy. Therefore, design for manufacturability techniques and tools are developed to preserve yield in the presence of manufacturing defects and circuit performance/power variability.Above all, the NaNoC design platform fosters the tight cooperation between system research, circuit design and process development by means of a silicon-aware decision making at each layer of the design hierarchy. In this direction, NaNoC not only provides a cross-layer approach to tackle composability challenges (e.g., physical design techniques for enhanced reliability combined with architecture-level techniques for fault containment), but also defines an exchange format for interoperability between design tools for cross-layer optimization. Interoperability between developed NoC design methods/prototype tools and mainstream design toolflows will also be pursued.

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