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REALITY

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Cerrado

Reliable and Variability tolerant System on a chip Design in More Moore Technolo...

Reliable and Variability tolerant System on a chip Design in More Moore Technologies As miniaturization of the CMOS technology advances designers will have to deal with increased variability and changing performance of devices. Intrinsic variability of devices which begins to be visible in 65nm devices already wil... ver más

31/08/2010

IMEC

4M€

Presupuesto del proyecto: 4M€

Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 6 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2010-08-31 No tenemos la información de la convocatoria

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Este proyecto no cuenta con búsquedas de partenariado abiertas en este momento.

Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

6 Participantes

IMEC

0.00€ | Lider

UNIBO

N.D. | Participante

UNIVERSITY OF GLASGOW

N.D. | Participante

STMICROELECTRONICS SRL

N.D. | Participante

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Líder del proyecto

INTERUNIVERSITAIR MICROELECTRONICA CENTRUM No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 4M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto As miniaturization of the CMOS technology advances designers will have to deal with increased variability and changing performance of devices. Intrinsic variability of devices which begins to be visible in 65nm devices already will become much more significant in smaller technologies. Soon it will not be possible to design systems using current methods and techniques.Scaling beyond the 32 nm technology node brings a number of problems whose impact on design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are becoming prominent issues.<br/>Dealing with these new challenges will require an adaptation of the current design process: a combination of design time and runtime techniques and methods will be needed to guarantee the correct functioning of Systems on Chip (SoC) over the product's lifetime, despite the fabrication in unreliable nano-scale technologies.The objective of this project is to develop design techniques and methods for real-time guaranteed, energy-efficient, robust and self-adaptive SoCs.The technological challenges to be tackled are:(a) Increased static variability and static fault rates of devices and interconnects;(b) Increased time-dependent dynamic variability and dynamic fault rates.(c) Build reliable systems out of unreliable technology while maintaining design productivity;(d) Deploy design techniques that allow technology scalable energy efficient SoC systems while guaranteeing real-time performance constraints.<br/>In order to tackle these challenges we focus our effort along two main axes:(a) Analysis of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions.(b) Solution techniques to mitigate impact of reliability issues of integrated circuits, at component, circuit, and architecture and system design.

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