Innovating Works

MADNESS

Financiado
Methods for predictAble Design of heterogeNeous Embedded System with adaptivity...
Methods for predictAble Design of heterogeNeous Embedded System with adaptivity and reliability Support The MADNESS project aims at the definition of innovative system-level design methodologies for embedded systems, able to drive the optimal composition of an heterogeneous MPSoC architecture, according to the requirements and the f... The MADNESS project aims at the definition of innovative system-level design methodologies for embedded systems, able to drive the optimal composition of an heterogeneous MPSoC architecture, according to the requirements and the features of a given target application field.<br/>The proposed methodologies will extend the classic concept of design space exploration, to cope with high heterogeneity, technology scaling, system reliability and multi-application demands, pursuing the following objectives:<br/>-Improve design predictability of highly heterogeneous embedded systems, bridging the so called "implementation gap", i.e. the gap between the results that can be predicted during the system-level design phase and those eventually obtained after the on-silicon implementation.<br/>-Consider, apart from more traditional constraints (typically, cost, performance, power consumption), continued availability of service, taking into account fault recovery as one of the optimization factors to be satisfied.<br/>-Support adaptive runtime management of the architecture.<br/>The technical approach of the project will rely on the following methods:<br/>-In order to improve the design predictability, traditional system-level design methodologies will be extended to consider variables strictly related with physical implementation of the architecture, leveraging a specific layer for rapid and accurate on-hardware FPGA-based emulation.<br/>-In order to address fault tolerance and adaptive runtime resources management, new methodologies are going to be defined and included in system-level exploration. Specific hardware/middleware IP modules will be developed to pursue those objectives.<br/>The results of the project are expected to have a deep impact on the design flow for high-complexity embedded systems, facilitating and enhancing the exploration of the architectural design space, therefore resulting in a significantly increased overall productivity. ver más
31/03/2013
UNICA
3M€

Línea de financiación: concedida

El organismo FP7 notifico la concesión del proyecto el día 2013-03-31
Presupuesto El presupuesto total del proyecto asciende a 3M€
Líder del proyecto
UNIVERSITA DEGLI STUDI DI CAGLIARI No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico TRL 4-5