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SecuReHLS

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EDA tools for Secure and Reliable High Level Synthesis Implementations

System on Chip (SoC) and Internet of Things (IoT) hardware accelerators are increasingly used in secure and critical applications, such as medical and automotive. For this reason, they need to have high levels of security and reli... ver más

14/02/2024

UNIVERSITY OF PIRA...

165K€

Presupuesto del proyecto: 165K€

Líder del proyecto

UNIVERSITY OF PIRAEUS RESEARCH CENTER No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2024-02-14

MSCA-IF-2019: Individual Fellowships

I+D

Cerrada hace 5 años

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Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

1 Participantes

UNIVERSITY OF PIRAEUS

165.09K€ | Lider

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Duración del proyecto: 46 meses Fecha Inicio: 2020-04-07
Fecha Fin: 2024-02-14

Líder del proyecto

UNIVERSITY OF PIRAEUS RESEARCH CENTER No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 165K€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto System on Chip (SoC) and Internet of Things (IoT) hardware accelerators are increasingly used in secure and critical applications, such as medical and automotive. For this reason, they need to have high levels of security and reliability at the same time. Hardware attacks are a serious threat for the security of hardware accelerators. Among them, Fault Attacks and Side Channel Attacks can breach even protected devices. Furthermore, injection of errors due to harsh environments may even lead to catastrophic failures of such accelerators. These threats are usually not concurrently addressed since their corresponding protections are not always compatible to each other. In a context, where designers use High Level Synthesis (HLS) flows to increase the productivity of designing hardware accelerators they must also ensure that security and reliability protections are taken into account by the HLS tools. In order to enable HLS flows to be the flow of choice for secure and reliable devices, we propose to provide to SoC and IoT designers, Electronic Design Automation (EDA) tools, capable to evaluate, improve and automate the insertion of protections during an HLS flow. Initially we will study the effects of HLS flows on the synthesis of manually protected high level descriptions. Afterwards, we will address concurrently security and reliability by automating the integration of compatible, countermeasures and mitigation techniques, inside the HLS flow, so as to automatically obtain secure and reliable RTL descriptions. Such tools and methodologies will help to minimize the corresponding overheads for protecting against each threat, while at the same time they will maintain the productivity of the HLS flow at high levels during the design of secure and reliable hardware accelerators.

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