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SafeSecS

Financiado

Cerrado

Abstractions for Safe and Secure HW SW Systems

Trains, planes, and other safety- and security-critical systems that our society relies on are controlled by computer systems, as is much of our critical infrastructure, including the power grid and cellular networks. But can we t... ver más

30/09/2026

USAAR

2M€

Presupuesto del proyecto: 2M€

Líder del proyecto

UNIVERSITAT DES SAARLANDES No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 2 Participantes

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2021-06-13

ERC-2020-ADG: ERC ADVANCED GRANT

I+D

Cerrada hace 4 años

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Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

2 Participantes

USAAR

2.45M€ | Lider

KAMAX

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Duración del proyecto: 63 meses Fecha Inicio: 2021-06-13
Fecha Fin: 2026-09-30

Líder del proyecto

UNIVERSITAT DES SAARLANDES No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 2M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto Trains, planes, and other safety- and security-critical systems that our society relies on are controlled by computer systems, as is much of our critical infrastructure, including the power grid and cellular networks. But can we trust in the safety and security of these systems? The starting point of SafeSecS is the observation that today’s hardware-software abstractions, instruction set architectures (ISAs), are fundamentally inadequate for the development of safe or secure systems. Indeed, ISAs abstract from timing, making it impossible to develop safety-critical systems that have to satisfy real-time constraints on top of them. Neither do ISAs provide sufficient security guarantees, making it impossible to develop secure systems on top of them. As a consequence, engineers are forced to rely on brittle timing and security models that are proven wrong time and again, as evidenced e.g. by the recent Spectre attacks; putting our society at risk. SafeSecS will attack the problem at its root by introducing a framework centered around hardware-software contracts that extend the guarantees provided by ISAs to capture key non-functional properties. Hardware-software contracts formally capture the expectations on correct hardware implementations and they lay the foundation for achieving safety and security guarantees as the software level. Below the hardware-software interface, SafeSecS will contribute modular design principles and tools to construct microarchitectures that provably satisfy a given hardware-software contract. Above the hardware-software interface, SafeSecS will develop rigorous, precise, and scalable techniques to guarantee key safety and security properties at the software level on top of hardware-software contracts. As a whole, SafeSecS will enable the systematic engineering of safe and secure hardware-software systems we can trust in.

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