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WAYTOGO FAST

Financiado

Which Architecture Yields Two Other Generations Of Fully depleted Advanced Subst...

Which Architecture Yields Two Other Generations Of Fully depleted Advanced Substrate and Technologies The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as wel... ver más

31/12/2017

STM CROLLES

99M€

Presupuesto del proyecto: 99M€

Líder del proyecto

STMICROELECTRONICS CROLLES 2 SAS No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Ver 32 Participantes

Financiación concedida El organismo FP6 notifico la concesión del proyecto el día 2017-12-31

Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:

ECSEL-02-2014: ECSEL Key Applications and Essential Technologies (IA)

I+D

Cerrada hace 10 años

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32 Participantes

STM CROLLES

Lider

UGR

N.D. | Participante

PICOSUN OY

N.D. | Participante

STMICROELECTRONICS FRANCE

N.D. | Participante

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Duración del proyecto: 31 meses Fecha Inicio: 2015-05-01
Fecha Fin: 2017-12-31

Líder del proyecto

STMICROELECTRONICS CROLLES 2 SAS

TRL 4-5

Presupuesto del proyecto 99M€

Descripción del proyecto The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.

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