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TIPS

financed

Closed

Thin Interconnected Package Stacks

The project TIPS aims at the conflation of embedding technologies for electronic components into extremely thin packages and the interconnection of those packages into stacked electronic systems. The testing of individual packages... see more

07/03/2012

MICROCHIP TECHNOLO...

4M€

Project Budget: 4M€

Project leader

MICROCHIP TECHNOLOGY CALDICOT LIMITED No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

PARTICIPATION DEPralty Sin fecha límite de participación.

Ver 5 Participantes

Financing granted El organismo FP7 notifico la concesión del proyecto The day 2012-03-07 We do not have the information of the call

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characteristics of the participant

Este proyecto no cuenta con búsquedas de partenariado abiertas en este momento.

Private Information

No hay información privada compartida para este proyecto. Habla con el coordinador.

5 Participantes

MICROCHIP TECHNOLOGY CALDICO...

0.00€ | Leader

IMEC

N.D. | participant

OTICON

N.D. | participant

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Project leader

MICROCHIP TECHNOLOGY CALDICOT LIMITED No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Project Budget 4M€

participation deadline Sin fecha límite de participación.

Project description The project TIPS aims at the conflation of embedding technologies for electronic components into extremely thin packages and the interconnection of those packages into stacked electronic systems. The testing of individual packages before stacking is performed will mitigate stacked package yield issues.Embedding of components will be developed starting from a basis of different technical approaches, depending on component type (active or passive), dimension and commercial availability. In order to reach the targeted stacked package thickness of 100 µm at maximum, the thickness of the embedded electrical components will be sub 50 µm.In this way modular thin packages will be realized, containing either arrays of or single electronic components. All packages have in common the same interface interconnection scheme to the next package. The interconnection scheme is to be developed in the project. The top and bottom package will have a layout for assembly of SMD components on the one hand or a ball grid array for soldering of the package stack onto a substrate board. Whether the packages stacks are interconnected within the stacking process or after stacking will be defined in the project. It is crucial to the outcome of the project that the stacking/interconnection is a highly robust process with an extremely low reject rate. Furthermore the realized package stacks have to withstand subsequent harsh process steps such as reflow soldering. Therefore early and continuous reliability testing of the packages as well as of packages stacks will be preformed.Viability and cost effectiveness of the developed technologies will be addressed throughout the development. In this way a future application of the technology will be more likely. Demonstrators for medical applications will be realized, where miniaturization and high functionality are the primary objectives.

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