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spOt

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Spin Orbit Torque memory for cache Multicore processor applications

The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption will soon start to limit microprocessor performance growth. The go... ver más

31/03/2016

CNRS

4M€

Presupuesto del proyecto: 4M€

Líder del proyecto

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 10 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2016-03-31 No tenemos la información de la convocatoria

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10 Participantes

CNRS

0.00€ | Lider

TLI

N.D. | Participante

KIT

N.D. | Participante

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Líder del proyecto

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 4M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption will soon start to limit microprocessor performance growth. The goal of the spOt project is to modify the memory hierarchy by the integration of non-volatility (NV) as a new feature of memory cache, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing.To accomplish this aggressive goal, limitations of present NV memories in terms of speed and endurance must be overcome and new architectures taking full benefit of these new functionalities must be developed. The consortium will base its research on a recent discovery achieved jointly by SPINTEC and ICN, called "Spin Orbit Torque" (SOT). This disruptive technology, which can be viewed as the ultimate evolution of Spin Transfer Torque, offers the same non-volatility and compliance with technological nodes below 22nm, with the addition of lower power consumption, cache-compatible high speed, and truly infinite endurance.To demonstrate its viability for cache, a number of identified technology roadblocks are addressed by the spOt project through its 5 work-packages and 4 intermediate goals: i) the realization of a fast write, low power, high read signal single memory cell ii) the development of a single cell architecture (standard cell) with minimal footprint iii) A stand-alone memory test chip with full functionality iv) The full chip simulation of a low-power/normally-off multicore processor.The final objective of the project is twofold: The fabrication of a SOT memory test chip, which would be benchmarked against existing and forecasted solutions in order to demonstrate the integrability and manufacturability of this new technology; The design and full chip simulation of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach.

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