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SQWIRE

Financiado

Cerrado

Silicon Quantum Wire Transistors

The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. The co-ordinator has demonstrated both theoretically and experimentally that nano... ver más

31/08/2013

UCC

4M€

Presupuesto del proyecto: 4M€

Líder del proyecto

UNIVERSITY COLLEGE CORK NATIONAL UNIVERSITY... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 9 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2013-08-31 No tenemos la información de la convocatoria

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Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

9 Participantes

UCC

0.00€ | Lider

MAGWEL

N.D. | Participante

CNRS

N.D. | Participante

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Líder del proyecto

UNIVERSITY COLLEGE CORK NATIONAL UNIVERSITY... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 4M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto The aim of the SQWIRE project is to develop a disruptive, industry-compatible CMOS technology based on novel silicon nanowire transistor structures. The co-ordinator has demonstrated both theoretically and experimentally that nanowire MOS transistors can be fabricated at wafer level using silicon-on-insulator (SOI) substrates. These novel devices have shown electrical properties that are comparable or even superior to those of regular transistors.Two such novel devices are the Gated Resistor (a junctionless transistor simulated, prototype fabricated and patented) and the variable-barrier tunnel transistor (VBT, simulated and patented). To obtain industrial validation, fabrication routes will be developed for these devices on novel 300 mm SOI wafers with silicon film thicknesses of only 10 nm. These routes will be underpinned by process development targeting atom-scale control of the silicon film thickness across the wafer.Device performance will be characterised at die-level and evaluated in a statistically meaningful manner at wafer level. The extracted parameters will serve as the basis for the development of a compact model of the Gated Resistor devices, which can be used for further circuit design and the validation of advanced numerical simulations.The fabrication process for the first device (Gated Resistor) is less complex and more flexible than that of regular transistors. It has the potential of increasing yield and reducing the price of integrated circuits. Furthermore, the Gated Resistor offers the promise of superior scaling to sub-22 nm dimensions compared to regular transistors. In addition, the process can easily be implemented in semiconductor materials other than silicon. The second device (Variable Barrier Transistor) is capable of providing subthreshold slopes sharper than any conventional transistor. This permits one to reduce the supply voltage of integrated circuits, and hence their energy consumption.

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