Revolutionary embedded memory for internet of things devices and energy reductio...
Revolutionary embedded memory for internet of things devices and energy reduction
REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and
variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :
i) Investigation...
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Información proyecto REMINDER
Duración del proyecto: 43 meses
Fecha Inicio: 2015-11-16
Fecha Fin: 2019-06-30
Líder del proyecto
UNIVERSIDAD DE GRANADA
No se ha especificado una descripción o un objeto social para esta compañía.
Total investigadores5511
Presupuesto del proyecto
5M€
Fecha límite de participación
Sin fecha límite de participación.
Descripción del proyecto
REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and
variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :
i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a
Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness
(variability), speed, reduced footprint and cost.
ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a
memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits,
blocks and architectures will be carefully analysed from the power-consumption point of view.
In addition variability tolerant design techniques underpinned by variability analysis and statistical
simulation technology will be considered.
iii) Demonstration of a system on chip application using the developed memory solution and
benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also
require the redesign of different applications, including memory cells, and therefore we also propose the evaluation
of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative
materials.
The fulfilment of the objectives above will also imply the development of:
i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will
allow us to improve the CMOS technology by boosting device performance.
ii) New behavioural models, incorporating variability effects, to reach a deep understanding of
nanoelectronics devices
iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.
iv) Extreme low power solutions
The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.