Hola,
¿eres nuevo aquí?

Regístrate gratis y conecta tu empresa con financiación pública, partners y proyectos.

Tengo cuenta

Regístrate

Ver video

REFLECT

Financiado

Cerrado

Rendering FPGAs to Multi Core Embedded Computing

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple co... ver más

31/12/2012

HISRO

4M€

Presupuesto del proyecto: 4M€

Líder del proyecto

HONEYWELL INTERNATIONAL SRO No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Fecha límite participación Sin fecha límite de participación.

Ver 7 Participantes

Financiación concedida El organismo FP7 notifico la concesión del proyecto el día 2012-12-31 No tenemos la información de la convocatoria

0% 73% 100%

Información adicional privada

No hay información privada compartida para este proyecto. Habla con el coordinador.

7 Participantes

HISRO

0.00€ | Lider

U.PORTO

N.D. | Participante

INESC ID

N.D. | Participante

TU Delft

N.D. | Participante

Proyectos interesantes

PTQ-09-02-01414

Electronics

Software

39K€ Cerrado

TIN2009-09806

Electronics

Software

95K€ Cerrado

PTQ-08-03-08502

Electronics

Software

84K€ Cerrado

PTQ-08-01-06854

Electronics

Software

72K€ Cerrado

PTQ-08-01-06854

Electronics

Software

72K€ Cerrado

PTQ-08-03-08410

Electronics

Software

54K€ Cerrado

Conecta tu I+D

¿Tienes un proyecto y buscas un partner? Gracias a nuestro motor inteligente podemos recomendarte los mejores socios y ponerte en contacto con ellos. Te lo explicamos en este video

Líder del proyecto

HONEYWELL INTERNATIONAL SRO No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Presupuesto del proyecto 4M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort.This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics.We expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.

Conecta tu I+D

Entra hoy

¿Olvidé mi contraseña?

Financiación

Empresas

CTIs/Universidades

Proyectos

Investigadores