Innovating Works

The European PILOT

Financiado
Pilot using Independent Local Open Technologies
Accelerators provide the majority of performance in modern High Performance Computing (HPC) systems and are the fundamental building blocks for Exascale systems. The European PILOT (Pilot using Independent Local & Open Technology)... Accelerators provide the majority of performance in modern High Performance Computing (HPC) systems and are the fundamental building blocks for Exascale systems. The European PILOT (Pilot using Independent Local & Open Technology) will be the first demonstration of two ALL European HPC and High Performance Data Analytics (HPDA) (AI, ML, DL) accelerators, designed, implemented, manufactured, and owned by Europe. The European PILOT combines open source software (SW) and open and proprietary hardware (HW) to deliver the first completely European full stack software, accelerator, and integrated ecosystem based on RISC-V accelerators coupled to any general purpose processor (CPU) via PCIe Gen 6.0 or CXL 3.0. This pilot will demonstrate key HPC and HPDA workloads and software stacks. The European PILOT is also the first to demonstrate an ALL European HPC ecosystem. The accelerators will be manufactured in the new European GlobalFoundries 12 nm advanced silicon technology, a major demonstration of European technology independence. The European PILOT combines cutting edge research utilizing SW/HW co-design to demonstrate HPC and HPDA accelerators running key applications and libraries in a full software stack including middleware, runtimes, compilers, and tools for the emerging RISC-V ecosystem. The European PILOT is able to produce a full stack (SW and HW) research prototype by leveraging and extending the work done in multiple European projects like: EPI, MEEP, POP2 CoE, EuroEXA, and ExaNeSt. This pre-production system can only be realized with a combination of existing IP, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software. Finally, while the applications we use span AI to HPC, the aggressive ASIC implementation (chip size and small geometry) will be the smallest technology node manufactured in Europe and can easily be adapted for a near-future HPC implementation. ver más
28/02/2026
BARCELONA SUPERCOM...
30M€
Duración del proyecto: 51 meses Fecha Inicio: 2021-11-17
Fecha Fin: 2026-02-28

Línea de financiación: concedida

El organismo H2020 notifico la concesión del proyecto el día 2021-11-17
Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:
EuroHPC-2020-01-a: Advanced pilots towards the European supercomputers
Cerrada hace 4 años
Presupuesto El presupuesto total del proyecto asciende a 30M€
Líder del proyecto
BARCELONA SUPERCOMPUTING CENTERCENTRO NACIONA... No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico TRL 4-5 118M