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ORIGENAL

Financiado

Origami electronics for three dimensional integration of computational devices

Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also ec... ver más

31/03/2024

BUW

3M€

Presupuesto del proyecto: 3M€

Líder del proyecto

BERGISCHE UNIVERSITAET WUPPERTAL No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Ver 6 Participantes

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2024-03-31

Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:

FETOPEN-01-2018-2019-2020: FET-Open Challenging Current Thinking

I+D

Cerrada hace 6 años

0% 100%

6 Participantes

BUW

334.13K€ | Lider

VISAN INDUSTRIAS ZOOTECNICAS

360.61K€ | Participante

VTT

960.00K€ | Participante

GESELLSCHAFT FUR ANGEWANDTE...

383.22K€ | Participante

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27-11-2024: DGIPYME En las últimas 48 horas el Organismo DGIPYME ha otorgado 1 concesiones

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Duración del proyecto: 55 meses Fecha Inicio: 2019-08-30
Fecha Fin: 2024-03-31

Líder del proyecto

BERGISCHE UNIVERSITAET WUPPERTAL

TRL 4-5

Presupuesto del proyecto 3M€

Descripción del proyecto Increasing the integrated circuits complexity by lateral scaling, known as Moore’s law, was the major driving force for the semiconductor industry. Now, after more than 4 decades down scaling is approaching fundamental and also economic limitations, and new solutions for further increasing the transistor count are explored. Utilizing the third dimension in chip architecture is one of the most promising directions. However, current solutions like wafer-to-wafer stacking will only deliver solutions for the short term with maximum some tens of layers on-top of each other’s. In the ORIGENAL project we propose a radically new approach to address the challenge of ultra-dense 3D integration of CMOS devices by using a thin-film-transistor (TFT) technology on thin foil substrate and the subsequent topological folding in order to achieve a dense 3D packaging with completely new integration architectures. This radically new approach will enable the stacking of thousands of layers on top of each other’s, each containing state-of-the-art CMOS circuits and thus will provide enough fuel to further increase the transistor count on a chip according to Moore’s law for more than 30 years. In addition, new computing concepts like neuromorphic computing will significantly benefit from the highly interconnected architecture developed in this project. The proposal focuses on the development of a suitable thin-film-transistor technology on ultrathin-foil, the 3D interconnect and architecture, and the required technology for high precision folding. Achieving the ambitious objectives requires an interdisciplinary approach including contributions from Material science, electrical engineering, mechanical engineering, biology, physics and chemistry. The proposed forefront research will not only lay the foundations for a new line of technology, but also open up an opportunity to reinforce the technological leadership of European players.

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