NanoRecycle
Financiado
On-chip waste recovery in quantum and nanoscale devices guided by novel performa...
On-chip waste recovery in quantum and nanoscale devices guided by novel performance quantifiers
Quantum and nanoscale technologies promise to revolutionise computing, sensing, information and communication applications. However, they are missing a dedicated effort towards energy sustainability exploiting their characteristic...
Quantum and nanoscale technologies promise to revolutionise computing, sensing, information and communication applications. However, they are missing a dedicated effort towards energy sustainability exploiting their characteristic properties. The theoretical project NanoRecycle addresses this important outstanding problem, by developing schemes for on-chip recovery of waste that typical device operations leave behind: in classical devices, this waste is often dissipated heat, but waste in nanoscale and quantum devices has characteristic nonthermal, fluctuating, and quantum properties. The scope of NanoRecycle is to develop processes converting this waste to electrical power or other resources that are useful for further on-chip tasks. The analysis will be based on sufficiently generic setups to capture the characteristic waste properties, that are at the same time typical elements of current quantum and nanotechnologies and are concretely connected to feasible, state-of-the-art experiments. This involves multi-terminal electronic conductors, but also hybrid devices coupling to microwave resonators.To guide the design, analysis, and optimisation of on-chip waste-recovery, my team and I will first capture and quantify the characteristic properties of the various types of waste and then put in place comprehensive performance quantifiers for the efficiency of dedicated conversion processes. An important performance goal of such a conversion in small-scale devices, which we will also account for in our performance analysis, is the output power precision (namely the suppression of power fluctuations), crucial for further on-chip use. While the power obtained from this waste recovery is expected to be small, its potential for contributing to energy-sustainable processes lies in the availability on-chip for further use, thereby circumventing high-loss attenuation procedures, which occur when bringing large classical fields down to the chip.
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Duración del proyecto: 59 meses
Fecha Inicio: 2024-01-01
Fecha Fin: 2028-12-31
Fecha Fin: 2028-12-31
Línea de financiación: concedida
El organismo HORIZON EUROPE notifico la concesión del proyecto el día 2024-01-01
Línea de financiación objetivo
El proyecto se financió a través de la siguiente ayuda:
ERC-2022-COG:
ERC CONSOLIDATOR GRANTS
Cerrada
hace 2 años
Presupuesto
El presupuesto total del proyecto asciende a
2M€
Líder del proyecto
CHALMERS TEKNISKA HOGSKOLA AB
No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico
TRL
4-5
Perfil tecnológico
TRL
4-5