Innovating Works

EXTRA

Financiado
Exploiting eXascale Technology with Reconfigurable Architectures
To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such comput... To handle the stringent performance requirements of future exascale High Performance Computing (HPC) applications, HPC systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require reconfiguration as an intrinsic feature, so that specific HPC application features can be optimally accelerated at all times, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in from the start. The idea is to enable the efficient co-design and joint optimization of architecture, tools, applications, and reconfiguration technology in order to prepare for the necessary HPC hardware nodes of the future. The project EXTRA covers the complete chain from architecture up to the application: • More coarse-grain reconfigurable architectures that allow reconfiguration on higher functionality levels and therefore provide much faster reconfiguration than at the bit level. • The development of just-in time synthesis tools that are optimized for fast (but still efficient) re-synthesis of application phases to new, specialized implementations through reconfiguration. • The optimization of applications that maximally exploit reconfiguration. • Suggestions for improvements to reconfigurable technologies to enable the proposed reconfiguration of the architectures. In conclusion, EXTRA focuses on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new reconfigurable architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a design concept, and applications that are tuned to maximally exploit run-time reconfiguration techniques. Our goal is to provide the European platform for run-time reconfiguration to maintain Europe’s competitive edge and leadership in run-time reconfigurable computing. ver más
31/08/2018
UGent
4M€
Duración del proyecto: 38 meses Fecha Inicio: 2015-06-29
Fecha Fin: 2018-08-31

Línea de financiación: concedida

El organismo H2020 notifico la concesión del proyecto el día 2018-08-31
Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:
FETHPC-1-2014: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
Cerrada hace 9 años
Presupuesto El presupuesto total del proyecto asciende a 4M€
Líder del proyecto
UNIVERSITEIT GENT No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico TRL 4-5