Innovating Works

ECOSCALE

Financiado
Energy efficient Heterogeneous COmputing at exaSCALE
In order to reach exascale performance current HPC servers need to be improved. Simple scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementa... In order to reach exascale performance current HPC servers need to be improved. Simple scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Apart from improvements in implementation technology, what is needed is to refine the HPC application development as well as the architecture of the future HPC systems. ECOSCALE tackles this challenge by proposing a scalable programming environment and hardware architecture tailored to the characteristics and trends of current and future HPC applications, reducing significantly the data traffic as well as the energy consumption and delays. We first propose a novel heterogeneous energy-efficient hierarchical architecture and a hybrid MPI+OpenCL programming environment and runtime system. The proposed architecture, programming model and runtime system follows a hierarchical approach where the system is partitioned into multiple autonomous Workers (i.e. compute nodes). Workers are interconnected in a tree-like structure in order to form larger Partitioned Global Address Space (PGAS) partitions, which are further hierarchically interconnected via an MPI protocol. Secondly, to further increase the energy efficiency of the system as well as its resilience, the Workers will employ reconfigurable accelerators that can perform coherent memory accesses in the virtual address space utilizing an IOMMU. The ECOSCALE architecture will support shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, and, more importantly, automated hardware synthesis of these resources from an OpenCL-based programming model. We follow a co-design approach that spans a scalable HPC hardware platform, a middleware layer, a programming and a runtime environment as well as a high-level design environment for mapping applications onto the system. A proof of concept prototype and a simulator will be built in order to run two real-world HPC applications and several benchmarks. ver más
31/07/2019
TELECOMMUNICATION...
4M€
Perfil tecnológico estimado
Duración del proyecto: 49 meses Fecha Inicio: 2015-06-29
Fecha Fin: 2019-07-31

Línea de financiación: concedida

El organismo H2020 notifico la concesión del proyecto el día 2019-07-31
Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:
FETHPC-1-2014: HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
Cerrada hace 10 años
Presupuesto El presupuesto total del proyecto asciende a 4M€
Líder del proyecto
EREVNITIKO PANEPISTIMIAKO INSTITOUTO TILEPIKO... No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico TRL 4-5