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DUALLOGIC

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Dual channel CMOS for sub 22 nm high performance logic

We propose to develop for the first time a dual-channel CMOS technology comprising high channel mobility (high-µ) Ge pMOS and III-V compound semiconductor nMOS transistors co-integrated on the same complex engineered substrate on... see more

31/05/2011

"NCSR ""D"""

9M€

Project Budget: 9M€

Project leader

NATIONAL CENTER FOR SCIENTIFIC RESEARCH DEMOK... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

PARTICIPATION DEPralty Sin fecha límite de participación.

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Financing granted El organismo FP7 notifico la concesión del proyecto The day 2011-05-31 We do not have the information of the call

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9 Participantes

"NCSR ""D"""

0.00€ | Leader

UNIVERSITY OF GLASGOW

N.D. | participant

KU Leuven

N.D. | participant

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Project leader

NATIONAL CENTER FOR SCIENTIFIC RESEARCH DEMOK... No se ha especificado una descripción o un objeto social para esta compañía.

TRL 4-5

Project Budget 9M€

participation deadline Sin fecha límite de participación.

Project description We propose to develop for the first time a dual-channel CMOS technology comprising high channel mobility (high-µ) Ge pMOS and III-V compound semiconductor nMOS transistors co-integrated on the same complex engineered substrate on Si. This offers a high performance booster as an option for the 22 nm technology creating competitive advantage for the European nanoelectronics industry. In addition, high-µ dual channel CMOS could be the main new introduction in sub-22 nm nodes in agreement with the strategic planning of the ENIAC technology platform. The project will develop the full set of FEOL modules from the starting local GeOI substrate to the dual-channel engineered substrate, the high-k/metal gate stacks and the S/D junctions with low resistivity contacts. Our aim is to use surface inversion channels and a self-aligned process with implanted S/D contacts for both III-V and Ge MOSFETs to ensure compatibility with the scaling and operation rules of CMOS. Device modelling and circuit design will assist in selecting the most suitable device architecture. The technology will be validated by the successful co-integration of short channel functional transistors using a 65 nm/200 mm pilot semiconductor processing line. This will allow characterization in terms of mobility at short gate lengths and identification of possible showstoppers associated with the behavior of high-µ channels at nanoscale dimensions. In addition, using toolsets, process flows and know how similar to Si, we aim at demonstrating that the high-µ dual channel technology is scalable and manufacturable without the need for introducing costly and disruptive technologies, thus ensuring the CMOS evolution for next generations. Mobilizing major technology development laboratories in Europe along with leading semiconductor and information technology industry and key semiconductor equipment manufacturers, this project can be a catalyst to the effort for maintaining competence in manufacturing and IP in Europe

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