Codasip RISC-V Solution f...
Financiado
Codasip High-end processor IP and high-level design tools for RISC-V
Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. R...
Codasip offers a unique combination of semiconductor processor IP based on the RISC-V open instruction set architecture (ISA) and high-level EDA tool Codasip Studio providing outstanding flexibility and 5x faster time to market. RISC-V ISA can be used for a wide variety of applications ranging from low power and low gate count embedded cores to advanced high frequency application cores. We are extending our portfolio of IP cores to include high-end high-performance compute area, complementing our cores that cover the power efficient embedded and mid range compute area: a new generation of advanced core with a 9-stage pipeline with out-of -order superscalar architecture called A90. The release of A90 will lead towards the A110 core with heavily speculative execution and an 11-stage pipeline.
The design of these cores will simultaneously trigger a release of Codasip Studio processor design tool for high-end compute, including advanced features like support of out of order architectures.
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Duración del proyecto: 33 meses
Fecha Inicio: 2022-10-26
Fecha Fin: 2025-07-31
Fecha Fin: 2025-07-31
Línea de financiación: concedida
El organismo HORIZON EUROPE notifico la concesión del proyecto el día 2022-10-26
Línea de financiación objetivo
El proyecto se financió a través de la siguiente ayuda:
HORIZON-EIC-2022-ACCELERATOROPEN-01:
EIC Accelerator Open
Cerrada
hace 1 año
Presupuesto
El presupuesto total del proyecto asciende a
22M€
Líder del proyecto
CODASIP GMBH
No se ha especificado una descripción o un objeto social para esta compañía.
Perfil tecnológico
TRL
4-5
Perfil tecnológico
TRL
4-5
19.75M€ |
Participante