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WiPLASH

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Architecting More Than Moore Wireless Plasticity for Heterogeneous Massive Com...

Architecting More Than Moore Wireless Plasticity for Heterogeneous Massive Computer Architectures The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory uni... ver más

30/09/2023

UPC

3M€

Presupuesto del proyecto: 3M€

Líder del proyecto

Universidad Politécnica de Cataluña No se ha especificado una descripción o un objeto social para esta compañía.

Total investigadores 9

Fecha límite participación Sin fecha límite de participación.

Ver 8 Participantes

Financiación concedida El organismo H2020 notifico la concesión del proyecto el día 2023-09-30

FETOPEN-01-2018-2019-2020: FET-Open Challenging Current Thinki... Specific Challenge:to lay the foundations for radically new future technologies of any kind from vis...

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Este proyecto no cuenta con búsquedas de partenariado abiertas en este momento.

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8 Participantes

UPC

351.38K€ | Lider

AGROPECUARIA OBANOS

262.54K€ | Participante

UNIBO

328.75K€ | Participante

RWTH AACHEN

423.44K€ | Participante

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Duración del proyecto: 48 meses Fecha Inicio: 2019-09-06
Fecha Fin: 2023-09-30

Líder del proyecto

Universidad Politécnica de Cataluña No se ha especificado una descripción o un objeto social para esta compañía.

Total investigadores 9

Presupuesto del proyecto 3M€

Fecha límite de participación Sin fecha límite de participación.

Descripción del proyecto The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability. In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.

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