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10ACe

Financiado

10 Angstrom CMOS exploration

The objective of the 10ÅCe pThe objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node,... ver más

30/04/2027

ASML NETHERLANDS B...

98M€

Presupuesto del proyecto: 98M€

Líder del proyecto

ASML NETHERLANDS B.V. No se ha especificado una descripción o un objeto social para esta compañía.

Ver 34 Participantes

Financiación concedida El organismo HORIZON EUROPE notifico la concesión del proyecto el día 2024-05-17

Línea de financiación objetivo El proyecto se financió a través de la siguiente ayuda:

HORIZON-KDT-JU-2023-1-IA-Topic-1: General according to ECS-SRIA 2022 (IA)

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34 Participantes

ASML NETHERLANDS B.V.

2.70M€ | Lider

COVENTOR SARL

254.53K€ | Participante

EVG

379.87K€ | Participante

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Últimas noticias

25-11-2024: ECE En las últimas 48 horas el Organismo ECE ha otorgado 52 concesiones

25-11-2024: CMVAMADRID En las últimas 48 horas el Organismo CMVAMADRID ha otorgado 1 concesiones

25-11-2024: FUNDACION-EOI En las últimas 48 horas el Organismo FUNDACION EOI ha otorgado 6 concesiones

Duración del proyecto: 35 meses Fecha Inicio: 2024-05-17
Fecha Fin: 2027-04-30

Líder del proyecto

ASML NETHERLANDS B.V.

Presupuesto del proyecto 98M€

Descripción del proyecto The objective of the 10ÅCe pThe objective of the 10ÅCe project is to explore and realize solutions for the 10Å CMOS chip technology. Its consortium covers the entire value chain for manufacturing of the CMOS chips in the 10A node, that is, from chip design to lithography to process technology and finally chip metrology. Essential parts of hardware, software and processing technology are developed pushing the boundaries of semiconductor design and manufacture to enable the new node and keep Moore’s law alive. The 10ÅCe project is built based on the following four pillars. Lithography Equipment: ASML and expert EUV partners Zeiss, FastMicro, IOM, Plasma Matters, TNO, TU/e, University of Twente and VDL-ETG will: • Increase key performance indicators of the EUV tool, to enable smaller pitches and increase yield. • Increase sustainability of the EUV tool, both during production as well as increasing the times a module in an EUV tool can be refurbished. Chip design and mask optimization: Imec with the involvement of expert imaging , CAD and IP design partners ARM, ASML and Siemens will: • Assess the impact of the introduction of 3D mCFET on chip design: in terms of power, performance and area. • Development of new computational lithography solutions to print 10Å CFET structures, to improve imaging by next generation mask design. Process Technology: As the ultimate device for logic, the CFET architecture is proposed and Imec and expert partners Coventor, EVG, IBS, Intel, JSR, LAM, RECIF, TEL, Zeiss and Wooptix will: • Demonstrate a fully functional monolithic CFET (mCFET) • Increase sustainability of the chip manufacturing process, across the manufacturing process and including resist material development. Process characterization: Applied Materials and expert partners Thermofisher, Nova, KLA and Bruker will: • Explore and realize high throughput and sample density per wafer, for the analysis, characterization for 10Å 3D CFET devices, interconnect and materials

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